Several solutions for stacking semiconductor chips exist. In a wire bond stack, one chip may be stacked onto another chip, and the electrical contacts between the two chips may be created by wire bonding. These wire bond stacks may have large dimensions and restricted electrical performance. In a flip chip wire bond stack, solder bumps may be placed on the top side of a chip, and the chip may be flipped so that the top side (having the solder bumps) may contact electrical contacts positioned on a substrate. A wire bonded chip may then be attached to the bottom of a flip chip, forming a stack. Additional chips stacked on the package would require wire bonding, resulting in a large package size and restricted electrical performance. In through silicon via (TSV) chip stacking, vias may extend (from the active side of a chip) through the chip to provide electrical connection to the inactive side of the chip. TSV technology, however, is costly, and the supply chain for TSV chips is still being developed. What is needed is a chip stacking technology that is potentially less expensive and results in a chip package that may be relatively small and may have superior electrical performance.